Fleet

26-Aug-2009: Marina is fully functional! All three chips from the third batch were packaged correctly, powered up, and completed the entire functional test suite. Yield, power, and performance data will be posted here over the course of the next two weeks.

What is Fleet?

Fleet is a clockless processor architecture which has been described as:

People often ask if Fleet is “a dataflow processor”. Fleet can be used to execute dataflow graphs, but it does not have random-access token buffers. Random-access token buffers are the defining feature (and bottleneck) in hardware dataflow processors; their omission has a profound impact on Fleet's programming model. Although Fleet does meet some definitions of “a dataflow processor,” such a characterization is misleading.

News

15-Jun-2010: Ivan's manifesto  Shifting the Paradigm: Twenty Cents Worth of History and accompanying video.

15-Feb-2010: A video demo of Marina.

17-Dec-2009: Adam and Ivan gave talks at ISI and Fulcrum Microsystems; slides are the same as those used for Ivan's CMU lecture.

15-Oct-2009:  Slides from Ivan's distinguished lecture at the Carnegie Mellon CS Department are now online.

07-Oct-2009:  Slides from Adam's talk at the Berkeley Wireless Research Center are now available.

26-Sep-2009: Performance numbers are now available for the Marina chip. It operated correctly up to 2.95 volts (the foundry only certifies its chips up to 1.3 volts); at 3.0 volts the chip suffered permanent damage. Although the chart below indicates that Marina is actually capable of executing 7.6 billion instructions per second (in a single-issue pipeline), keep in mind that at the higher voltages there are significant power consumption and cooling issues that make it impractical to run a commercial product in that range.

07-Sep-2009: The  slides from Adam's August 24th talk at Portland State are now online.

28-Aug-2009: The abstract and  slides from Adam's August 28th talk at Galois are now online.

27-Aug-2009: The slides from Adam's talk at Sun Labs titled The Omega Counter: A 15Ghz Kessels Counter with 20ps/bit Settling Time in TSMC 40nm CMOS are now  online.

26-Aug-2009: Marina is fully functional! All three chips from the third batch were packaged correctly, powered up, and completed the entire functional test suite. Yield, power, and performance data will be posted here over the course of the next two weeks.

19-Aug-2009: Packaged chips are in the lab right now. We've been having a few difficulties getting the wires bonded correctly. Progress can be tracked here.

07-Aug-2009: The chips are back! It'll still be a few weeks before we have them packaged and wired up in the lab, though.

08-Jul-2009: The  abstract and  slides from Ivan's talk on 07-Jul-2009 are now available.

22-Jun-2009: The Marina test chip has taped out!. It should come back in mid-August, with testing starting in early September. In the meantime, check out:

07-Apr-2009: We have successfully run a merge sort on the cycle-accurate Fleet simulator (using a Xilinx ML509). The video framebuffer presents the same interface as a Memory ship; when the demo program starts it is populated with scrambled pixels. See this image for an explanation of the pixel format. The contents of video memory is then sorted, yielding the final image. A video of the demo is available.

12-Dec-2008/08-Jan-2009: Switch to git, “gitweb” interface.

26-Jun-2008: FleetCode 1.0 has been released! Click here for more details.

Documents

If you're new to Fleet, the best introduction is:

You can find several relevant publications and memos here.

Instructions for uploading your own memos (requires an @EECS account).

Contact

 Adam Megacz.